1. Field of the Invention
The present invention relates to a semiconductor memory device which includes a multipurpose terminal receiving an address signal and a data signal and automatically refreshes a memory cell.
2. Description of the Related Art
In recent years, a semiconductor memory called a pseudo-SRAM has been attracting attention. The pseudo-SRAM includes DRAM memory cells (dynamic memory cells) and operates as an SRAM by internally automatically performing a refresh operation of the memory cells. The dynamic memory cell is small in area. Therefore, the pseudo-SRAM with a low cost per bit and a large capacity can be developed.
The pseudo-SRAM generates an internal refresh request to perform the refresh operation in a predetermined cycle independently of (in asynchronization with) an external access request (read request or write request.) In Japanese Unexamined Patent Application Publication No. 2001-243765, a pseudo SARM with a built-in arbiter which determines priority between the internal refresh request and the external access request to prevent a collision between the refresh operation and an access operation is described.
Meanwhile, a semiconductor memory device which receives an address signal and a data signal at the same terminal is proposed. The formation of a multipurpose terminal reduces the number of terminals, which reduces a chip size and thereby lowers the manufacturing cost. This type of semiconductor memory device includes an address valid terminal which receives an address valid signal to recognize that the address signal is supplied to the multipurpose terminal. A system which accesses the semiconductor memory device sets the address valid terminal to a valid level when supplying the address signal to the multipurpose terminal, and sets the address valid terminal to an invalid level when supplying the data signal to the multipurpose terminal.
The present invention is made to solve the following problems which arise when a multipurpose terminal receiving an address signal and a data signal is provided in a pseudo-SRAM.
Generally, when receiving activation of a chip enable signal, the pseudo-SRAM recognizes an external access request. A system which accesses the pseudo-SRAM needs to supply an access address at the time of the external access request. Accordingly, if the multipurpose terminal is formed in the pseudo-SRAM, the system needs to set an address valid terminal, together with a chip enable terminal, to a valid level when accessing the pseudo-SRAM. In other words, in a state where the chip enable terminal is fixed to the valid level, the address valid signal is recognized as the external access request.
However, the above arbiter of the pseudo-SRAM recognizes the external access request by only the chip enable signal. Therefore, when the chip enable signal is fixed to the valid level, the arbiter cannot recognize the external access request and continues to give priority to a refresh request. This causes contention between a refresh operation and an access operation, and thereby the pseudo-SRAM malfunctions.
When the address signal is received by the multipurpose terminal, the valid period of the address signal becomes shorter. A semiconductor memory device malfunctions if an erroneous address signal is incorporated thereto. Further, when an internal circuit of the semiconductor memory device is operated using the address signal with a short valid period, the timing margin of the internal circuit reduces, which makes a circuit design difficult. If the timing margin reduces, the semiconductor memory device becomes more likely to be affected by a change in manufacturing condition, resulting in a decrease in yield.
In the pseudo-SRAM, an external address signal or an internally generated refresh address signal needs to be selected as the address signal to be supplied to a memory cell array depending on whether the access operation is performed or the refresh operation is performed. If the valid period of the external address is short, the timing margin to select the address signal reduces. If the erroneous address signal is selected, the semiconductor memory device malfunctions.
When a semiconductor memory device which includes the multipurpose terminal receiving the address signal and the data signal is newly designed, a design cost and a manufacturing cost of a photomask and so on are newly required. These costs are reduced by appropriating already existing design property.